Shift Register

Class Diagram

The UML diagram of Fig. 8 shows the overview of the class.

@startuml class sc_core::sc_module class shift_register<int width> { .. Inputs .. sc_in_clk clk sc_in<sc_logic> data_in .. Outputs .. sc_out<sc_lv<width> > q .. Variables .. sc_lv<width> q_state __ Processes __ prc_shift_register() } shift_register -up-|> sc_core::sc_module @enduml

Fig. 8 Shift Register Class Diagram

Class Description

template<int width>
class shift_register

Clock Divider module with clock division ratio

sc_core::sc_in_clk clk

Input clock

sc_core::sc_in<sc_core::sc_logic> data_in

Input data to be shifted in

sc_core::sc_out<sc_core::sc_lv<width>> q

Stored value of the shift register

sc_core::sc_lv<width> q_state

Internal stored value

void prc_shift_register(void)

Shift register main process

Shifts the value one bit to the left and assign data_in to the MSb.

list sensitivity

clk.pos()

Structure

Fig. 9 shows the structure of the generic shift register. Our implementation doesn’t differ from the generic shift register.

../_images/shift_register_circuit.png

Fig. 9 Shift Register Circuit

Simulation Results

The code of the test case of the shift_register is shown below;

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static const int reg_width = 5;

SC_TEST(shift_register) {
  sc_signal<sc_logic> data_in;
  sc_signal<sc_lv<reg_width> > register_state;
  sc_clock sys_clock("sys_clock", clock_period, clock_duty, clock_start, false);

  ...

  shift_register<reg_width> sregister ("ShiftRegister");

  ...

  data_in = sc_logic('0');
  sc_start(50, SC_NS);
  data_in = sc_logic('1');
  sc_start(100, SC_NS);
  data_in = sc_logic('0');
  sc_start(100, SC_NS);
}

Note

  • data_in starts at sc_logic(‘0’)
  • data_in toggles to sc_logic(‘1’) at \(50ns\)
  • data_in toggles back to sc_logic(‘0’) at \(100ns\)
  • Shift Register width is \(5\)

Fig. 10 shows the result of the simulation.

../_images/shift_register_simulation.png

Fig. 10 Shift Register Simulation Wave Result

Note

  • At \(50ns\) the shifting of sc_logic(‘1’) starts. The sc_logic(‘1’) is injected at the MSb.
  • Between \(120ns\) and \(150ns\) the value of register_state[4:0] stays constant at \(0x1F\) because of the shift register’s width is set to \(5\).
  • After \(150ns\) the shifting of sc_logic(‘0’) starts
  • 5 clock cycles after \(150ns\) the register_state[4:0] is back to \(0x0\).